PIC18F258 |
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CONFIG1H (address:0x300001, mask:0x27) |
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OSC -- Oscillator Selection bits |
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OSC = LP |
0xF8 |
LP oscillator. |
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OSC = XT |
0xF9 |
XT oscillator. |
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OSC = HS |
0xFA |
HS oscillator. |
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OSC = RC |
0xFB |
RC oscillator. |
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OSC = EC |
0xFC |
EC oscillator w/ OSC2 configured as divide-by-4 clock output. |
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OSC = ECIO |
0xFD |
EC oscillator w/ OSC2 configured as RA6. |
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OSC = HSPLL |
0xFE |
HS oscillator with PLL enabled/Clock frequency = (4 x FOSC). |
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OSC = RCIO |
0xFF |
RC oscillator w/ OSC2 configured as RA6. |
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OSCS -- Oscillator System Clock Switch Enable bit |
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OSCS = ON |
0xDF |
Oscillator system clock switch option is enabled (oscillator switching is enabled). |
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OSCS = OFF |
0xFF |
Oscillator system clock switch option is disabled (main oscillator is source). |
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CONFIG2L (address:0x300002, mask:0x0F) |
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PWRT -- Power-up Timer Enable bit |
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PWRT = ON |
0xFE |
PWRT enabled. |
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PWRT = OFF |
0xFF |
PWRT disabled. |
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BOR -- Brown-out Reset Enable bit |
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BOR = OFF |
0xFD |
Brown-out Reset disabled. |
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BOR = ON |
0xFF |
Brown-out Reset enabled. |
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BORV -- Brown-out Reset Voltage bits |
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BORV = 45 |
0xF3 |
VBOR set to 4.5V. |
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BORV = 42 |
0xF7 |
VBOR set to 4.2V. |
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BORV = 27 |
0xFB |
VBOR set to 2.7V. |
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BORV = 25 |
0xFF |
VBOR set to 2.5V. |
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CONFIG2H (address:0x300003, mask:0x0F) |
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WDT -- Watchdog Timer Enable bit |
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WDT = OFF |
0xFE |
WDT disabled (control is placed on the SWDTEN bit). |
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WDT = ON |
0xFF |
WDT enabled. |
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WDTPS -- Watchdog Timer Postscale Select bits |
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WDTPS = 1 |
0xF1 |
1:1. |
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WDTPS = 2 |
0xF3 |
1:2. |
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WDTPS = 4 |
0xF5 |
1:4. |
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WDTPS = 8 |
0xF7 |
1:8. |
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WDTPS = 16 |
0xF9 |
1:16. |
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WDTPS = 32 |
0xFB |
1:32. |
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WDTPS = 64 |
0xFD |
1:64. |
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WDTPS = 128 |
0xFF |
1:128. |
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CONFIG4L (address:0x300006, mask:0x85) |
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STVR -- Stack Full/Underflow Reset Enable bit |
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STVR = OFF |
0xFE |
Stack Full/Underflow will not cause Reset. |
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STVR = ON |
0xFF |
Stack Full/Underflow will cause Reset. |
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LVP -- Low-Voltage ICSP Enable bit |
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LVP = OFF |
0xFB |
Low-Voltage ICSP disabled. |
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LVP = ON |
0xFF |
Low-Voltage ICSP enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins. |
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CONFIG5L (address:0x300008, mask:0x0F) |
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CP0 -- Code Protection bit |
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CP0 = ON |
0xFE |
Block 0 (000200-001FFFh) code protected. |
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CP0 = OFF |
0xFF |
Block 0 (000200-001FFFh) not code protected. |
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CP1 -- Code Protection bit |
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CP1 = ON |
0xFD |
Block 1 (002000-003FFFh) code protected. |
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CP1 = OFF |
0xFF |
Block 1 (002000-003FFFh) not code protected. |
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CP2 -- Code Protection bit |
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CP2 = ON |
0xFB |
Block 2 (004000-005FFFh) code protected. |
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CP2 = OFF |
0xFF |
Block 2 (004000-005FFFh) not code protected. |
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CP3 -- Code Protection bit |
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CP3 = ON |
0xF7 |
Block 3 (006000-007FFFh) code protected. |
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CP3 = OFF |
0xFF |
Block 3 (006000-007FFFh) not code protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Boot Block Code Protection bit |
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CPB = ON |
0xBF |
Boot Block (000000-0001FFh) code protected. |
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CPB = OFF |
0xFF |
Boot Block (000000-0001FFh) not code protected. |
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CPD -- Data EEPROM Code Protection bit |
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CPD = ON |
0x7F |
Data EEPROM code protected. |
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CPD = OFF |
0xFF |
Data EEPROM not code protected. |
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CONFIG6L (address:0x30000A, mask:0x0F) |
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WRT0 -- Write Protection bit |
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WRT0 = ON |
0xFE |
Block 0 (000200-001FFFh) write protected. |
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WRT0 = OFF |
0xFF |
Block 0 (000200-001FFFh) not write protected. |
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WRT1 -- Write Protection bit |
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WRT1 = ON |
0xFD |
Block 1 (002000-003FFFh) write protected. |
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WRT1 = OFF |
0xFF |
Block 1 (002000-003FFFh) not write protected. |
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WRT2 -- Write Protection bit |
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WRT2 = ON |
0xFB |
Block 2 (004000-005FFFh) write protected. |
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WRT2 = OFF |
0xFF |
Block 2 (004000-005FFFh) not write protected. |
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WRT3 -- Write Protection bit |
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WRT3 = ON |
0xF7 |
Block 3 (006000-007FFFh) write protected. |
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WRT3 = OFF |
0xFF |
Block 3 (006000-007FFFh) not write protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Configuration Register Write Protection bit |
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WRTC = ON |
0xDF |
Configuration registers (300000-3000FFh) write protected. |
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WRTC = OFF |
0xFF |
Configuration registers (300000-3000FFh) not write protected. |
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WRTB -- Boot Block Write Protection bit |
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WRTB = ON |
0xBF |
Boot Block (000000-0001FFh) write protected. |
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WRTB = OFF |
0xFF |
Boot Block (000000-0001FFh) not write protected. |
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WRTD -- Data EEPROM Write Protection bit |
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WRTD = ON |
0x7F |
Data EEPROM write protected. |
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WRTD = OFF |
0xFF |
Data EEPROM not write protected. |
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CONFIG7L (address:0x30000C, mask:0x0F) |
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EBTR0 -- Table Read Protection bit |
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EBTR0 = ON |
0xFE |
Block 0 (000200-001FFFh) protected from Table Reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 (000200-001FFFh) not protected from Table Reads executed in other blocks. |
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EBTR1 -- Table Read Protection bit |
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EBTR1 = ON |
0xFD |
Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks. |
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EBTR2 -- Table Read Protection bit |
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EBTR2 = ON |
0xFB |
Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks. |
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EBTR2 = OFF |
0xFF |
Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks. |
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EBTR3 -- Table Read Protection bit |
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EBTR3 = ON |
0xF7 |
Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks. |
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EBTR3 = OFF |
0xFF |
Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Boot Block Table Read Protection bit |
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EBTRB = ON |
0xBF |
Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks. |
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